In the field of integrated circuit manufacture, recent and continuing advances allow for semiconductor structures to be fabricated of increasingly smaller dimensions. For example, gate electrodes for insulated-gate field effect transistors (IGFETs) of widths below one micron are commonly being manufactured, with the fabrication of transistors with smaller than one-half micron gate electrodes expected in the foreseeable future. As is well known, the ability to fabricate increasingly small transistors allows for the manufacture of integrated circuits with larger numbers of functions per unit area. In addition, such smaller IGFETs provide increasingly higher transconductance values, so that circuit functions implemented with such devices operate with faster switching speeds.
As is well known in the art, short channel length IGFETs are vulnerable to certain performance and reliability problems. A first one of such problems is the so-called "hot electron", or "hot carrier" effect, where high-energy carriers are generated by high electric fields at the drain junction, become trapped in the gate dielectric, and cause a threshold voltage shift. Another problem to which short channel length IGFETs are particularly prone is the so-called "short-channel effect", which increases sub-threshold leakage between drain and source. In addition, source and drain depletion regions become closer to one another as the transistor sizes decrease, reducing the punch-through voltage for such devices.
It is known that the use of graded source/drain junctions improves the susceptibility of modern IGFETs to each of these problems, as the localized electric field at the metallurgical junctions is lower for a graded junction relative to an abrupt junction. A well-known conventional technique for fabricating graded junction metal-oxide-semiconductor field-effect transistors (MOSFETs) implants a lightly doped source/drain region self-aligned with the gate electrode, and uses a sidewall insulator spacer on the sides of the gate to space the heavily doped source/drain implant back from the edge of the lightly-doped region, resulting in a graded junction. An example of this technique is described in U.S. Pat. No. 4,356,623. Another technique for forming a graded junction n-channel MOSFET implants two species which have different diffusion rates in the source/drain locations, so that a graded junction results after diffusion; such a technique is described in U.S. Pat. No. 4,851,360 and in U.S. Pat. No. 4,878,100.
While graded junctions according to these methods reduce the deleterious effects observed in short-channel abrupt junction transistors, each method provides the equivalent of a series resistor at the drain end of the channel (and, in conventional processes, also at the source end). The presence of this additional series resistance reduces the performance of the transistors and the circuits implemented thereby. As described in Izawa et al., "Impact of the Gate-Drain Overlapped Device (GOLD) for Deep Submicrometer VLSI", Trans. Electron Devices, Vol. 35, No. 12 (IEEE, 1988), pp. 2088-93, a transistor with a gate electrode which overlaps the graded drain region provides for the reduction in the high-electric field short-channel problems noted above, but without significant loss of transistor performance.
Prior techniques for fabricating such overlapping gate electrode transistors, commonly referred to as "inverted-T" transistors, have either been quite complex or require extremely precise process conditions, with little room for error. The Izawa et al. paper noted hereinabove forms the inverted-T gate by relying on a thin native oxide layer, formed by exposure of the first polysilicon layer to air, as an etch stop in the etching of the upper poly layer which, as noted therein, requires highly selective dry etching. Due to the thinness and poor integrity of polysilicon native oxide, it is believed that reliance on native oxide as an etch stop will provide little process margin and poor manufacturability.
Another method for forming an inverted-T gate structure is described in Pfiester, et al., "A Self-Aligned LDD/Channel Implanted ITLDD Process With Selectively-Deposited Poly Gates for CMOS VLSI", International Electron Device Meeting, Paper 32.2.1 (IEEE, 1989), pp. 769-772. This method first forms a thin polysilicon layer which will overlap the LDD regions. An oxide layer is then formed over this layer, and removed from the locations at which the gate electrode is to be formed. Selective polysilicon deposition then forms the gate electrode is formed at the locations from which the oxide has been removed, with no polysilicon forming elsewhere.
Another method for forming an overlapping gate structure is described in Chen, et al., "A Highly Reliable 0.3 .mu.m N-channel MOSFET Using Poly Spacers", 1990 Symposium on VLSI Technology (IEEE, 1990), pp. 39-40. This paper describes the use of polysilicon spacers instead of oxide spacers, where native oxide on the sides of the polysilicon gate electrode is sufficiently damaged during source/drain implant that the spacers are electrically connected to the gate electrode.
By way of further background, as structures in devices such as IGFETs become increasingly smaller, the series resistance of the narrow conductors therein increase. This is particularly true for sub-micron gate electrodes and source/drain regions. A well-known technique for increasing the conductivity of these structures is the direct reaction of a refractory metal, such as tantalum, titanium, cobalt, tungsten and the like, with the silicon of the gate electrodes and source-drain regions to form a highly conductive metal silicide cladding thereat. It is known that sidewall oxide spacers, as noted hereinabove in the formation of graded drain junctions, provide electrical isolation between the gate electrode and the source/drain regions, as the silicide will not form thereover, allowing a subsequent etch to remove unreacted metal from over the oxide spacers while not significantly disturbing the silicide. An example of a method of forming a silicide-clad transistor in such a manner is described in U.S. Pat. No. 4,384,301. The formation of silicide-cladding in such a manner is commonly referred to in the art as "salicide", referring to the self-aligned nature of the silicide to the conductive structures.
In prior self-aligned silicidation, however, since the same sidewall spacer is used to define the graded junction, or "lightly-doped-drain" ("LDD") region and the separation of the source/drain silicide from the gate silicide, selection of the desired spacer width may not be optimized for either. Particularly for transistors of channel lengths less than one-half micron, it is contemplated that the spacing required for the LDD region will be less than that necessary to maintain isolation between the source/drain silicide and the gate electrode silicide. According to the prior techniques for defining the sidewall spacer thickness, providing a thick enough sidewall spacer to maintain electrical isolation between the silicid layers would require a longer LDD region; accordingly, the benefits of silicidation in such transistors will come at a cost of increased device size, and reduced performance due to the longer than desired LDD regions in series with the transistor channel.
It is therefore an object of this invention to provide an improved method of forming an IGFET with its gate electrode overlapping the drain region.
It is a further object of this invention to provide such a method which has improved robustness for manufacturing.
It is a further object of this invention to provide a method of forming a silicide-clad IGFET with graded junction, where the silicide spacing is optimized independently from the size of the graded junction region.
It is a further object of this invention to provide a method of forming a overlapping gate transistor with silicide cladding, where the silicide spacing may be optimized independently from the size of the graded junction region.
Other objects and advantages will be apparent to those of ordinary skill in the art having reference to the following specification, in combination with the drawings.